Part 4 Tau Law in Practice — From Kirin to Kunpeng to Ascend

In the first three parts, we explored the theory, the engineering, and the interconnect architecture behind Huawei's post-Moore strategy. But a theory is only as good as the silicon it produces. This installment examines how Tau Law principles have been applied across Huawei's chip portfolio — from smartphone SoCs to server processors to AI accelerators — and what the results tell us about the trajectory of this approach.

The Guiding Principle Across All Chips

Before diving into specific products, it is important to understand a unifying thread: every chip Huawei has developed since 2019 has been guided by the same core philosophy — reduce τ (signal delay) at every level, using design innovation to compensate for process node constraints.

This is not a single technique applied uniformly. It is a design mindset that manifests differently depending on the chip's purpose, workload characteristics, and system context. The specific tools vary — Logic Folding, 3D stacking, custom bus architectures, heterogeneous integration — but the optimization target is always the same: make signals travel faster and shorter.

Kirin: The Smartphone Proving Ground

The Kirin smartphone SoC is where Tau Law principles are most visible to consumers, because smartphone chips face the tightest constraints of all — limited physical space, strict thermal budgets, and the need to balance performance with battery life.

The Kirin 9000S Baseline (2023)

When the Kirin 9000S launched, it was built on a mature process node and ran at approximately 2.6 GHz. By the standards of Moore's Law, this chip was not competing at the frontier of process technology. But it demonstrated something important: through architectural optimization, a mature-node chip could deliver a competitive user experience.

The Kirin 9000S was the first major product to apply early-stage Logic Folding techniques. The results were visible in real-world usage — responsive UI performance, acceptable thermal behavior, and battery life that did not suffer despite the absence of an advanced process node.

The Kirin 9030 Pro (2025)

By 2025, the Kirin 9030 Pro pushed the frequency to 2.75 GHz while maintaining thermal and power discipline. The incremental frequency gain may look modest on paper, but in the context of a mature process node with no access to EUV lithography, every 100 MHz of frequency improvement represents a significant engineering achievement.

The gains came from refined Logic Folding patterns, improved inter-layer via design, and tighter hardware-software co-scheduling — all core Tau Law techniques.

The Next-Generation Kirin (2026)

The next-generation Kirin chip, expected to debut with the Mate 90 series in fall 2026, represents the most complete implementation of Tau Law principles in a smartphone SoC to date. Key targets include:

• Peak frequency of 3.1 GHz — a substantial jump achieved primarily through Logic Folding's reduction of critical signal path delays.

• Transistor density of 238 MTr/mm² — approaching advanced-node density through spatial restructuring rather than geometric shrinking.

• Energy efficiency improvement of over 40% — shorter signal paths mean less energy wasted on wire resistance and capacitance.

He Tingbo has described the expected improvements as "leapfrog" in performance, integration density, and transistor density. Whether the market perceives it as a true leap will depend on real-world benchmarks, but the engineering trajectory is clear: each generation extracts more performance from the same process node through design innovation.

Kunpeng: Scaling Tau Law to the Data Center

Smartphone chips are constrained by thermal and power budgets. Data center processors face a different set of pressures — massive core counts, high memory bandwidth requirements, and the need to scale across thousands of chips in a server cluster.

Kunpeng, Huawei's server processor line, applies Tau Law principles at a different scale and with different priorities:

Core-to-core communication. In a high-core-count processor, the latency of communication between cores is a critical performance factor. Kunpeng applies Logic Folding and custom on-chip interconnect design to minimize core-to-core delay, ensuring that multi-threaded workloads scale efficiently.

Memory controller optimization. Memory access latency is one of the largest sources of τ in a server processor. Kunpeng's memory controller architecture has been progressively optimized to reduce the delay between core request and data delivery, a direct application of temporal scaling at the chip level.

Multi-socket interconnect. For servers that use multiple Kunpeng processors on a single motherboard, the inter-socket communication link is a potential bottleneck. Huawei's custom interconnect architecture — a precursor to the Lingqu philosophy — reduces cross-socket latency, enabling tighter coupling between processors.

The Kunpeng line demonstrates that Tau Law is not limited to mobile chips. Its principles scale to the data center, where system-level interconnect optimization can have outsized impact on real-world workload performance.

Ascend: AI Acceleration Under Process Constraints

AI accelerators face perhaps the most demanding performance requirements of any chip category. Training large language models requires thousands of accelerators working in tight synchronization, exchanging massive volumes of gradient data with minimal latency. Any delay in inter-accelerator communication directly translates to longer training times and higher costs.

Ascend, Huawei's AI computing chip line, applies Tau Law principles with particular intensity:

On-chip data movement. AI workloads are characterized by massive parallel data movement — weights, activations, and gradients flowing between compute units, memory, and interconnect interfaces. Ascend's on-chip architecture has been optimized to minimize the delay of these data flows, using Logic Folding to bring frequently communicating units into close physical proximity.

Inter-chip communication. For AI training clusters, the interconnect between accelerators is often the bottleneck. Ascend chips are designed to integrate seamlessly with Huawei's high-speed interconnect architecture, enabling low-latency, high-bandwidth communication across thousands of accelerators. This is where the Lingqu Bus Protocol's principles become critical — extending the temporal scaling philosophy from within a single chip to across an entire AI cluster.

Memory bandwidth optimization. AI workloads are often memory-bandwidth-bound rather than compute-bound. Ascend's memory subsystem has been progressively optimized to reduce the latency of memory access, ensuring that compute units are not starved for data.

The Ascend line illustrates how Tau Law's system-level philosophy — optimizing delay from device to system — is essential for AI computing, where the interconnect is often the limiting factor rather than raw compute power.

The Cumulative Picture: 381 Chips and Counting

Across all product lines — optical communication, data communication, wireless, 5G, smartphones, autonomous driving, general computing, and AI computing — Huawei has independently developed and mass-produced 381 chips guided by Tau Law principles over the past six years.

This number is significant for two reasons:

Breadth of application. Tau Law is not a niche technique applicable to one type of chip. It is a general-purpose design philosophy that has been applied across the full spectrum of semiconductor products. This breadth suggests that the underlying principles are robust and transferable.

Iterative learning. Each chip generation provides data that informs the next. The Logic Folding patterns that work well for a smartphone SoC may need adjustment for an AI accelerator, but the fundamental optimization target — reduce τ — remains constant. Six years of iterative application across 381 chips represents a deep well of engineering knowledge.

The Roadmap Ahead

Huawei has published specific targets that illustrate the trajectory of Tau Law's impact:

2029 — Peak frequency of 4 GHz. Achieving 4 GHz on a mature process node through temporal scaling alone would be a significant milestone. For context, many advanced-node chips today operate in the 3.5–4.5 GHz range, but they benefit from the fastest available process technology. Reaching 4 GHz without EUV lithography would demonstrate the power of design-driven performance scaling.

2031 — 1.4nm-equivalent transistor density on mature nodes. This is the most ambitious target. Through the combination of temporal scaling and Logic Folding, Huawei aims to achieve transistor density on mature process nodes that is equivalent to what the industry considers 1.4nm-class technology. If achieved, this would effectively decouple performance leadership from lithography equipment access — a profound shift in the semiconductor industry's competitive dynamics.

One-Sentence Summary

Tau Law is not a theoretical exercise — it is a living design philosophy that has shaped 381 chips across every product category, with each generation extracting more performance from the same process node through relentless optimization of signal delay.