Filling the domestic RISC-V CPU gap! StarFive's TianShu-100 officially delivered: server chips are no longer limited to x86 and Arm.

StarFive Technology recently officially launched the server-grade RISC-V HPC CPU core design, the Dubhe-100. This is the first server-grade RISC-V CPU IP in China to reach a deliverable state, and it has already been adopted by customers and entered the server chip development phase.

RISC-V has long been confined to the IoT and embedded fields, with high-performance server IP mostly remaining at the prototype validation stage. The official delivery of the Dubhe-100 fills the gap in domestic RISC-V high-performance computing IP.

In terms of performance specifications, the Dubhe-100 is benchmarked against the Arm Cortex-A78, achieving an integer IPC of SPECint2006 15/GHz. It adopts a deep out-of-order execution architecture, equipped with a 15-stage pipeline, 6-wide issue, and a 256-instruction out-of-order window.

This processor core strictly adheres to the RVA23 specification and is the first to implement an industry-leading out-of-order execution vector unit (RVV). Compared to similar products that only support in-order RVV execution, it avoids pipeline stalls caused by single long-latency instructions when handling vector-intensive tasks such as AI inference and scientific computing.

The CPU core supports single-core, dual-core, and quad-core cluster configurations, as well as mainstream interconnect bus protocols including TileLink, AXI, ACE, and CHI. It can interface with StarFive's self-developed NoC IP, the StarNoC-700, allowing expansion to 256 cores on a single die.

Additionally, the Dubhe-100 has completed full support for Type 1 and Type 2 Hypervisors, with the Linux operating system and KVM virtualization solutions both running stably on this platform.

In terms of commercial deployment, LECARC has confirmed it will adopt the Dubhe-100 as its base core to develop a new generation of server CPUs targeting intelligent edge applications.

StarFive Technology has also simultaneously launched server-grade infrastructure IP such as AIA (Advanced Interrupt Architecture) and IOMMU, further refining the underlying technology stack for intelligent computing centers. This marks RISC-V's true transition from the embedded domain into the server market.