Intel unveils Wildcat Lake chip: up to 40 TOPS of compute power, 64% lower power consumption.

Intel has officially unveiled technical details for its entry-level processor Wildcat Lake (Core Series 3), as reported by Wccftech.

This series targets the entry-level PC market, retaining Panther Lake's foundational architecture while optimizing packaging processes, reducing die area, streamlining I/O configurations, and improving motherboard design to effectively lower overall platform costs.

In terms of performance metrics, Wildcat Lake delivers up to 40 TOPS of platform-level AI compute, a 2.7x improvement over the previous-generation Raptor Lake U Refresh (Core 100 series). Creative and productivity performance can improve by up to 2.1x, while processor power consumption drops by 64%.

Regarding packaging, Intel has not adopted the Foveros 3D stacking technology used in Panther Lake (Core Ultra Series 3), instead shifting to organic multi-chip packaging (MCP) with UCIe (Universal Chiplet Interconnect Express) interconnect solutions to reduce packaging costs and yield losses.

MCP involves vertically stacking or horizontally arranging multiple functional dies, all packaged onto a single organic substrate carrier board.

UCIe, as an open standardized chiplet interconnect specification for the semiconductor industry, defines communication protocols between different chips within the same package, enabling chips from different vendors and process nodes to integrate flexibly like building blocks.

In terms of process selection, Wildcat Lake's compute die uses Intel's 18A process, while the I/O die is produced on TSMC's N6 process. The 18A process natively supports UCIe connectivity for the dual-die configuration.